Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to connect the die to higher level circuitry.
Semiconductor manufacturers strive to reduce the size of die packages to fit within the space constraints of electronic devices while increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power and/or storage capacity of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies using through-silicon vias (TSVs). A Hybrid Memory Cube (HMC) is one particularly useful device that includes a plurality of memory dies stacked on the top of a logic die.